The Challenges:
Making the ALU device was quite simple; all I had to do was follow the instructions on the course website. The foundation of the ALU was a 1-Bit ALU, which was used to make a 2-Bit ALU, which was used to make a 4-Bit ALU, which was made to make an 8-Bit ALU, which was used to make the 16-Bit ALU. The designs for all the ALUs are as follows:
1-Bit ALU:
2-Bit ALU:
4-Bit ALU:
8-Bit ALU:
After the ALU was finished, I had to wire the ADD lines. This took 5 different AND Gates ( one each Sub-Clock line 3-7), plus some very tricky wiring. This was probably the trickiest part of this proccessor so far. The wiring un-did a lot of wiring from earlier, and a lot of it involved changing wirings from before. After finally getting the wiring working, I tested out my device...it didn't work.
I left this lab for a while and came back to it. I started from scratch with the wiring, and when I was finsihed, my processor had completely stopped working. After pulling my hair out for a a few hours, I discover that I had flipped a Register around the wrong way, and this had completly messed up my processor. After flipping it around, the READ and WRITE lines worked again, but the ADD line was only outputting XXXX. Obviously there was something wrong.
I set the ZReg to be constantly erasing itself, and it was outputting 0000, so there was something wrong internally (with the ALU). I went back and found out that there was something wrong with it: I had mislabled a set of lines, and that was causing the messed-up output. After recreating my ALU device, everything worked!
The test run went as follows:
|
Line #
|
Before Test Run
|
After Test Run
|
|
0
|
FFFF
|
FFFF
|
|
1
|
6100
|
6100
|
|
2
|
7200
|
7200
|
|
3
|
6101
|
6101
|
|
4
|
7201
|
7201
|
|
5
|
1200
|
1200
|
|
6
|
7202
|
7202
|
|
7
|
0000
|
0000
|
|
100
|
ABCD
|
ABCD
|
|
101
|
1234
|
1234
|
|
200
|
0000
|
ABCD
|
|
201
|
0000
|
1234
|
|
202
|
0000
|
BE01
|
Difficulty Rating ( out of 5):
This lab was by far the most difficult one so far.
( 5 out of 5)