Lab #6: The LDG Instruction


Lab Date: February 25 , 2005

Due Date: February 27 , 2005

Date Posted: February 16 , 2005

Lab Link: http://www.wadanet.com/hasegawa/cs212s05/lab6-1.htm

Description:

Add The G-REG And Wire The LDG Instruction

What We Need To Make:

- A Buffer 12 Device

- A 4 Way "0" Device

- The G-REG ( A General Purpose 16-Bit REG)

- A Very Complicated Wiring

The Challenges:

The First Thing I Did Was Make A "1" and "0" Device. I Got The Idea From Scott's "Switches of Doom", And Thought I Would Make My Own. While I Haven't Had Any Major Problems With Accidentily Flipping Binary Switches, I Did Notice The My Schematic Was Starting To Fill Up With Binary Switches. I Was Having Trouble Distinguishing One From The Other. So, Rather Than Suffer Later, I Created My Own "0" and "1" Devices.

Next Up, I Had To Make A Three-State Four "0" Device. Using My Handy New "0" Device, This Was A Snap. All I Had To Do Was Add Som Three-State Buffer, And It Was Done.

Now Comes The Frustrating Part. I Attached The 0x4 Device, and A 12-Bit Reg...I Now Know That I Was Supposed To Use A 12-Way Buffer T.S., But I'll Get Back To That Later.

I Attached My Devices, And Wired Everything Up The Way That The Lab Showed. After Doing This, I Tried Running My Test PROM Program. Obviously, It Didn't Work. But It Wasn't The Unneccessary Register That Was Messing Things Up. The IR Wasn't Getting Any Input, And Absolutely Nothing Was Happening. After Searching Through My Design, I Couldn't Quite Figure It Out. So, I Left It.

The Next Day...

I Continued To Search For The Elusive Bug In My Processor. After Some Tinkering With The Cycle Speed (ie Slowing It Waaaaaaaay Down And Watching Exactly What Was Happening), I Found The Problem. For Some Reason (Which I Still Can't Figure Out), My Processor Had Slowed Down. So, I Had To Alter The Delays On One Of The Buffers, And Everything Was Working (Well, Everything that I Had Working Before).

Now, I Knew That My IR Was Working, But LDG Was Not. I Slowed Down The Speed Again And Noticed That The Lower 12-Bits From The IR Were Not Loading Onto The BUS. At This Point, I Realized That I Shouldn't Be Using A REG. Looking At The Lab Manual Gain Confirmed My Suspicions: I Was Supposed To Be Using A Buffer, Not A Register.

Designing The Buffer Was Easy, And I Was Surprised That I Didn't Have One In My Library.


After This, The Rest Was Easy. I Had To Alter Another Delay Because The GREG Was Trying To Load To Early, So Changing The Delay From 3 to 5 Fixed The Problem.

Final Product:

 

Difficulty Rating (out of 5):

The Wiring Was The Hardest Part Of This Lab, And I Could Have Finished This In Half The Time If I Had Read The Directions Carefully. I Don't Like Having To Increase The Amount Of Time On Those Two Buffers, Thought; I Hope That It Isn't An Indication Of Some Other Problem.

( 3 out of 5)